The present invention relates generally to integrated circuit (IC) memory devices, and more specifically, to a complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell and sense amplifier.
One commonly known DRAM cell is of the type that uses a single transistor to access data stored in a capacitor as a charge. A memory circuit formed from an array of these DRAM cells can have a single bit line serving all of the cells in a given column of the array. In this manner, data stored in one of the DRAM cells in the memory circuit can be read from the cell's capacitor through its respective bit line in response to a word line activating the cell. Single transistor DRAM cells that are deployed in a memory circuit with each having a word line that activates the cell are subject to high levels of stress during activation and inactivation. This can degrade the performance of the memory circuit. In particular, every time that one of these single transistor DRAM cells is turned on and off, the cells' respective word line can have voltage swings greater than 2.0 Volts (V). For example, consider a “high” logic level used in a digital circuit that can be represented by 1.0 V and a “low” logic level that can be represented by 0 V. In order to ensure that a good value is read out of the DRAM cell (e.g., a charge transfer of about 70% of the charge from the cell capacitor to the bit line), 1.5 V is typically applied to the transistor associated with the cell by its word line for activation. Because a DRAM cell is subject to charge leakage, -0.4 V is typically applied to the transistor by the word line during shut off of the transistor in order to minimize source to drain leakage. This negative voltage will shut off the transistor harder, enabling it to have an acceptable retention time. A 2 V swing across the gate of the transistor to facilitate such “hard” activations and shut-offs creates excessive stress for the transistor.
A CMOS DRAM cell is one type of DRAM that has been proposed to address the word line swing issues associated with the single transistor DRAM cell that deploys its own word line. One type of CMOS DRAM cell uses an n-type field-effect transistor (NFET) and a p-type field-effect transistor (PFET) to access data that is stored in a capacitor. A memory circuit formed from an array of these CMOS DRAM cells can have a single bit line serving all of the cells in a given column of the array. In this manner, data stored in a capacitor in one of the CMOS DRAM cells in the memory circuit can be accessed through either the cell's NFET or PFET, and be read and written to, by the bit line associated with the cell, in response to a word line activating the cell.
CMOS DRAM cells that are deployed in a memory circuit to have a word line that activates the NFET and a separate word line to activate the PFET are not subject to voltage swings at the gates of the transistors that cause high levels of stress during their activation and inactivation. In particular, the word line at the NFET will only need to swing from a negative voltage (e.g., −0.35 V) to a supply voltage during its activation and inactivation, while the PFET will only need to swing from a positive voltage (e.g., 1.5 V) to ground during its activation and inactivation. The swing on the word line in this configuration is reduced in comparison to the DRAM cell with the single transistor. However, this type of CMOS DRAM cell configuration doubles the capacitance on the bit line because more transistors are coupled to it. This reduces the charge transfer ratio and associated bit line signal. In addition, when the bit line is precharged to ground, a silicon-on-insulator (SOI) PFET body of the device leaks low, causing degradation to the off current and hence degraded retention. Similarly, when the bit line is precharged to a supply voltage, an SOI NFET body of the device leaks high, causing degradation to the off current and hence degraded retention. For the above reason, the single bit line configuration is less desirable to use with a CMOS DRAM cell.